China’s AI Chip IPO Frenzy Rolls On as Moore Threads Soars 210%

TL;DR Shanghai’s STAR Market delivered another blockbuster semiconductor debut as GPU maker Moore Threads surged 210% on day one, illustrating how Beijing’s capital markets are pouring limitless liquidity into domestic silicon alternatives despite ongoing lithography and packaging constraints.

The opening bell at the Shanghai Stock Exchange this morning triggered something between an investor stampede and an act of state-sponsored defiance.

Trading was halted twice for volatility within the first forty minutes as shares of domestic graphics and AI processor designer Moore Threads skyrocketed by 210% above their issue price. By midday in Shanghai, the company’s market capitalization crossed 180 billion yuan ($25.4 billion), turning its executive suite into overnight paper billionaires and generating the most lucrative semiconductor listing in Asia so far in 2026.

This is not an isolated speculative frenzy. Following hot on the heels of Biren Technology’s own oversubscribed public offering earlier this summer, the listing confirms that China’s domestic AI hardware sector has entered a self-funding acceleration phase. Cut off from advanced Western silicon by successive waves of United States export controls against China administered by the Department of Commerce, mainland venture capital, state guidance funds, and retail investors have banded together to build a parallel compute economy.

For international observers watching Nvidia navigate restricted variants like the H20 and its subsequent regional revisions, the message from Shanghai is unambiguous: Washington’s chip sanctions did not suffocate China’s domestic accelerator ambitions. Instead, they guaranteed domestic startups a captive, highly capitalized, and politically protected home market.

The STAR Market’s Infinite Liquidity Well

To understand how a fabless chipmaker with fractional revenue compared to Western incumbents can command a massive valuation, one must look at the mechanics of the Shanghai Sci-Tech Innovation Board, better known as the STAR Market.

Established to fast-track national champions in core technologies, the STAR Market functions as an equity-based sovereign wealth deployment vehicle. Domestic hyperscalers—including Alibaba, Tencent, and Baidu—are actively pressured by regulatory mandates to diversify away from American architectures and dedicate a growing share of their capital expenditure to locally designed processors.

Investors see an ironclad government guarantee. When enterprise buyers are legally and commercially incentivized to purchase domestic accelerators, traditional underwriting models based on free cash flow take a back seat to sovereign urgency. While Western capital has cooled toward late-stage startups that cannot show imminent path-to-profitability, China’s secondary market is treating any semiconductor firm with an operational tensor core as a non-negotiable strategic asset.

advanced microchip silicon die macro view — Photo by Brian Kostiuk on Unsplash

Moore Threads, founded by former Nvidia global vice president James Zhang, had been placed on the US Entity List alongside its domestic peers in late 2023. At the time, industry analysts predicted that being severed from Taiwan Semiconductor Manufacturing Company (TSMC) would render the firm’s roadmap obsolete. Instead, state-backed syndicates stepped in, bankrolling complex architectural redesigns to fit the capabilities of domestic foundries and overseas alternative packaging nodes.

The result is an aggressive pipeline of server GPUs designed specifically to power the massive clusters driving enterprise ai infrastructure throughout mainland China.

Benchmarks vs. Reality: Where Chinese Silicon Sits in 2026

The commercial viability of China’s GPU class relies on how closely these chips can approximate modern Western performance without access to the world’s most sophisticated lithography.

The industry consensus heading into late 2026 is nuanced: Chinese domestic processors have largely solved raw floating-point compute density for medium-scale training and widespread inference, but they remain bottlenecked by inter-chip interconnects, high-bandwidth memory (HBM) yields, and software friction.

Metric / Specification	Nvidia H100 (SXM5, 2023 Baseline)	Nvidia B200 (Blackwell, Global)	Huawei Ascend 910C (2025/2026 Domestic)	Moore Threads MTT S5000 (2026 STAR Spec)
Process Node	TSMC 4N (5nm class)	TSMC 4NP	SMIC N+2 / N+3 (7nm DUV)	Domestic multi-patterning 7nm
FP16 / BF16 Tensor TFLOPS	~1,979 (Dense)	~4,500 (Dense)	~1,400 (Dense)	~1,150 (Dense)
Memory Architecture	80GB HBM3	192GB HBM3e	64GB–96GB HBM2e / Domestic HBM	64GB HBM2e / High-Speed GDDR7 Array
Memory Bandwidth	3.35 TB/s	8.0 TB/s	~1.8–2.2 TB/s	~1.6 TB/s
Interconnect Bandwidth	NVLink 4 (900 GB/s)	NVLink 5 (1.8 TB/s)	HCCS (~390 GB/s)	MT-Link 2.0 (~400 GB/s)
Primary Software Ecosystem	CUDA	CUDA	CANN	MUSA (Meta-Enterprise Unified System Architecture)

While Moore Threads’ flagship MTT S5000 cannot match the sheer throughput of Nvidia’s Blackwell architecture, it sits comfortably within striking distance of older Ampere and baseline Hopper units for mainstream AI workloads. In large language model (LLM) fine-tuning and retrieval-augmented generation (RAG) deployments, three MTT S5000 units can perform the work of an imported, supply-constrained accelerator—provided the engineering team can handle the software overhead.

Crucially, the unit economics inside China do not follow global market forces. Because compute access is a sovereign bottleneck, domestic cloud providers are willing to absorb higher power bills and deploy wider cluster topologies to compensate for single-card performance deltas.

The Software Chasm: Breaking CUDA’s Gravity

Silicon is only as capable as the compiler that targets it. The true defensive moat protecting Nvidia has never been just its lithography or its tensor cores; it is CUDA, the software platform developed over two decades that anchors modern computer science curricula, enterprise libraries, and scientific frameworks.

Chinese GPU vendors have taken two distinct routes to navigate this software chasm:

1. Direct API Emulation and Translation Layers: Moore Threads has championed its MUSA architecture, which incorporates an automated translation pipeline that ingests native CUDA C++ code and maps it down to MUSA runtime instructions. While initial iterations suffered from crippling translation penalties, the 2026 revisions of the platform achieve 75% to 85% bare-metal performance for common PyTorch and vLLM operators.
2. Proprietary Ecosystem Enclaves: Huawei has taken a more radical approach with CANN (Compute Architecture for Neural Networks), actively discouraging CUDA reliance and partnering directly with domestic universities to build a walled-garden software stack tailored exclusively to Ascend silicon.

The sheer volume of open-source artificial intelligence models has inadvertently assisted China’s domestic silicon makers. The global pivot toward standardized runtime layers—such as OpenAI’s Triton compiler and modular framework abstraction in PyTorch 2.x—has lowered the barrier to entry. Hardware teams no longer need to reverse-engineer thousands of bespoke CUDA kernels by hand; they can target open intermediate representations, significantly shortening the time required to bring new chips to useful production duty.

Packaging, Lithography, and the Advanced Node Dilemma

Despite the euphoria on the Shanghai trading floor, China’s AI chip sector operates under hard physical constraints.

Domestic chip designers cannot legally place orders with TSMC, Samsung Foundry, or Intel Foundry. They rely almost entirely on mainland foundries like Semiconductor Manufacturing International Corporation (SMIC). Without commercial access to extreme ultraviolet (EUV) lithography systems manufactured by the Netherlands’ ASML, domestic foundries are forced to push deep ultraviolet (DUV) immersion lithography to its absolute thermodynamic limits through self-aligned quadruple patterning (SAQP).

semiconductor packaging manufacturing machine in electronics factory — Photo by Homa Appliances on Unsplash

This approach is commercially brutal. Multi-patterning DUV involves multiple exposure passes, radically inflating mask counts, increasing defect rates, and gutting wafer yields. In high-performance enterprise GPUs, where die sizes often exceed 500 square millimeters, wafer defects can quickly push unit fabrication costs into unsustainable territory.

To circumvent raw lithography limits, Chinese chip designers have turned aggressively to chiplet architectures and advanced multi-die packaging, utilizing domestic packaging specialists like JCET to combine smaller, high-yielding compute tiles on passive silicon interposers.

The strategy is effective, but it encounters another barrier: High Bandwidth Memory (HBM). With global supplies of advanced HBM3e concentrated among SK Hynix, Samsung, and Micron, mainland designers must either source legacy HBM2e through regional intermediaries or configure dense arrays of high-speed GDDR memory. The trade-off is measurable in thermal dissipation, board footprint, and cluster-level power consumption.

The Bifurcated Future of Global Compute

Moore Threads’ stellar IPO is not proof that China has won the semiconductor war; rather, it proves that the war has decisively partitioned the global technology sector into two mutually exclusive ecosystems.

In the West, computing power is concentrating around hyper-efficient, capital-intensive megaclusters running Blackwell-class architectures, optimized for extreme scale, lowest power per token, and seamless integration with emerging future tech platforms.

In China, compute is being industrialized through brute-force engineering, state-subsidized capital, and architectural workarounds. By underwriting companies like Moore Threads, Biren, and their supply chain partners on public exchanges, Beijing is creating an entire technology stack that is permanently insulated from future Western export controls.

The investors bidding up Moore Threads to triple-digit gains on day one are not betting that Chinese GPUs will displace Nvidia in Silicon Valley, Tokyo, or Frankfurt. They are betting that China’s domestic digital economy—spanning industrial robotics, sovereign foundation models, smart cities, and autonomous fleets—will need hundreds of thousands of accelerators every quarter, and will be legally required to buy them from home.

On that thesis, the market has delivered its verdict: the capital is here, the buyers are ready, and the parallel compute universe is officially open for business.